A typical method for manufacturing semiconductor wafers such as silicon wafers includes a slicing step of slicing a semiconductor ingot into disklike wafers; a chamfering step of chamfering the outer periphery of each wafer for the purpose of preventing cracking or chipping of the wafers; a lapping step of planarizing the wafers; an etching step of removing mechanical damage remained in the surface layer of each wafer; a polishing step of mirror-polishing the surface of each wafer; and a cleaning step of removing contaminants such as polishing agents or foreign matters adhered in the polishing step. When necessary, steps such as a heat treatment or grinding can be further conducted in the above steps. Furthermore, the sequence of the above steps can be altered, or a step can be repeated.
By the way, as making to high integration of semiconductor devices have been achieved in recent years, processes such as STI (shallow trench isolation) are used as micro device fabrication techniques. Therefore, in order to form circuitry patterns on the surface of a silicon wafer, an insulator film that is more even and has a uniform thickness is required. Then, for example, a method for planarizing an insulator film by CMP (chemical mechanical polishing) is used in the processes for manufacturing semiconductor devices.
Conventionally, micro uneven shapes (hereafter, referred to as waviness) on semiconductor wafer surfaces do not affect the processes for manufacturing semiconductor devices. However, in the STI, convex parts are selectively polished by CMP. Thus there occurs a problem that an insulator film has an uneven thickness due to the waviness.
The waviness is indicated by a parameter called nanotopography. The nanotopography is an indicator which show the flatness of a wafer surface, and indicates waviness within a spatial wavelength of 0.1 mm to several tens of mm of a wafer surface in a state of non-adsorption.
The nanotopography is generally measured with an apparatus such as a Nanomapper from ADE Corporation, a NanoPro from KLA-Tencor Corporation, or a Dynasearch from RAYTEX CORPORATION. These apparatus are optical types and the nanotopography is measured by using surface reflection of an object to be measured. Therefore, a wafer to be measured is required to have a mirror surface having a high reflectivity to some extent. Consequently, polished wafers are generally measured in terms of nanotopography.
By the way, in order to evaluate a process of slicing wafers from a semiconductor ingot, there are disclosed techniques of measuring the surface profile of a wafer in the state of as-cut, namely not being processed after being sliced (see Japanese Patent Application Laid-open (kokai) No. 07-106387; and Published Japanese Translations of PCT International Publication No. 2002-538447). In this way, wafers in the state of as-cut are measured for the purpose of evaluating the surface profile of the wafers in the state of as-cut and adjusting slicing conditions so as not to cause the waviness on slicing because the waviness generated on slicing can remain even after the wafers are subjected to subsequent processes such as lapping or polishing. Conventional parameters of representing surface conditions measured in the state of as-cut are warpage, warp, and the like.
However, the parameters based on the surface conditions of a wafer measured in the state of as-cut are not in correlation with nanotopography of the surface of the wafer after being polished. Therefore, in order to evaluate nanotopography of a wafer surface, it is necessary to conduct the evaluation after the wafer is subjected to a polishing step.
Therefore, in order to increase the efficiency of manufacturing wafers, there is a desire for a method in which nanotopography can be evaluated in a stage of a manufacturing process as early as possible.